     PRESERVE8 

    IMPORT TCD_System_Stack
    IMPORT TCT_System_Limit
    IMPORT INC_Initialize
    IMPORT Enable_TCM
    IMPORT Initialize_TCM
    IMPORT _fp_init
    IMPORT __rt_lib_init

    IMPORT |Load$$RAM_DATA$$Base|        
    IMPORT |Image$$RAM_DATA$$Base|       
    IMPORT |Image$$RAM_DATA$$Length|     
    IMPORT |Image$$RAM_DATA$$ZI$$Base|   
    IMPORT |Image$$RAM_DATA$$ZI$$Length| 
    IMPORT |Image$$RAM_DATA$$ZI$$Length|

    EXPORT DoVectorReset
    EXPORT End_of_Stacks
    EXPORT Initialize_memory_system
    EXPORT USR_Stack, End_of_Stacks, ABORT_Stack



   AREA Startup_bss, DATA, READWRITE, NOINIT
   ALIGN


























































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































SVC_STACK_SIZE    	EQU		0x1000
IRQ_STACK_SIZE    	EQU		0x400
FIQ_STACK_SIZE    	EQU		0x80
USR_STACK_SIZE    	EQU		0x400
UNDEF_STACK_SIZE    	EQU		0x80
ABORT_STACK_SIZE    	EQU		0x80

End_of_Stacks
SVC_Stack_End	 % SVC_STACK_SIZE 			
SVC_Stack                 							
IRQ_Stack_End  	 % IRQ_STACK_SIZE       		
IRQ_Stack                    						
USR_Stack_End     % USR_STACK_SIZE   			
USR_Stack                  						
UNDEF_Stack_End	% UNDEF_STACK_SIZE 			
UNDEF_Stack              							
ABORT_Stack_End	% ABORT_STACK_SIZE     		
ABORT_Stack                          					

    AREA IRAM_Stack, DATA, READWRITE, NOINIT
    ALIGN

FIQ_Stack_End      % FIQ_STACK_SIZE 			
FIQ_Stack         								


  AREA    ExternalFlashSection, CODE, READONLY
  ENTRY
_ENTRY

DoVectorReset 

    MRS     a1,CPSR
    BIC     a1,a1,#0x1F
    ORR     a1,a1,#0x13
    ORR     a1,a1,#(0x80 | 0x40)
    MSR     CPSR_cxsf,a1

   mrc   p15,0,a1,c1,c0,0
   ldr   a2,=(0x1 << 0)
   bic   a1,a1,a2
   ldr   a2,=(0x1 << 2):OR:(0x1 << 12):OR:(0x1 << 1)
   orr   a1,a1,a2
   mcr   p15,0,a1,c1,c0,0
   mcr  p15, 0, a1, c7, c7, 0

    LDR    r1,=(0x700C1000 + 0x000)
    LDR    r1,[r1]
    TST    r1, #(1 << 26)
    BEQ    %321

    BL Enable_TCM
    BL Setup_System_Stacks
    MOV    r0, #0
    IMPORT GSMExit
    BL     GSMExit
321

    MOV    r0,#0xffffffff
    LDR    r1,=(0x700C1000 + 0x00C)
    STR    r0,[r1]
   mov   r4,#0x1f
   b     %1
0  mov   r0,#0
   mov   r1,r4,lsl #0x2
   add   r1,r1,#0x70000000
   add   r1,r1,#0xc1000
   str   r0,[r1,#0x18]
   sub   r4,r4,#0x1
1  cmp   r4,#0x0
   bgt   %0

    BL Initialize_memory_system

    BL Enable_TCM

    BL Initialize_TCM

    BL Setup_System_Stacks 

    BL _fp_init
    BL __rt_lib_init

    BL INC_Initialize 

Initialize_memory_system
    LDR    r0, =|Load$$RAM_DATA$$Base|        
    LDR    r1, =|Image$$RAM_DATA$$Base|       
    LDR    r3, =|Image$$RAM_DATA$$ZI$$Base|   

    CMP    r1, r3
    BEQ    %1
0   CMP    r1, r3
    LDRCC  r2, [r0], #4
    STRCC  r2, [r1], #4
    BCC    %0

1   LDR    r1, =|Image$$RAM_DATA$$ZI$$Base|       
    LDR    r2, =|Image$$RAM_DATA$$ZI$$Length|     
    ADD    r1, r1, r2
    SUB    r1, r1, #64                            
    MOV    r2, #0                        
2   CMP    r3, r1
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    BCC    %2
    LDR    r1, =|Image$$RAM_DATA$$ZI$$Base|       
    LDR    r2, =|Image$$RAM_DATA$$ZI$$Length|     
    ADD    r1, r1, r2                             
    MOV    r2, #0
3   CMP    r3, r1
    STRCC  r2, [r3], #4
    BCC    %3

    BX      LR


Setup_System_Stacks

    MOV    r1,lr

    MOV     r0, #0x17:OR:0x80:OR:0x40 
    MSR     cpsr_cxsf, r0
    LDR     sp, =ABORT_Stack
    LDR     sl, =ABORT_Stack_End

   MOV     r0, #0x1B:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =UNDEF_Stack
   LDR     sl, =UNDEF_Stack_End

   MOV     r0, #0x11:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =FIQ_Stack
   LDR     sl, =FIQ_Stack_End

   MOV     r0, #0x12:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =IRQ_Stack
   LDR     sl, =IRQ_Stack_End

   MOV     r0, #0x13:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =SVC_Stack
   LDR     r0, =TCD_System_Stack 
   STR     sp, [r0, #0] 
   LDR     sl, =SVC_Stack_End 
   LDR     r0, =TCT_System_Limit 
   STR     sl, [r0, #0]

   MOV     r0, #0x1F:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =USR_Stack
   LDR     sl, =USR_Stack_End

   MOV     r0, #0x13:OR:0x80:OR:0x40
   MSR     cpsr_cxsf, r0

   BX      r1

    END
