     PRESERVE8 

    IMPORT pcu00bmcr0
    IMPORT IRAM_RO_EndPtr
    IMPORT IRAM_RO_StartPtr
    IMPORT InitialHWConfig  
    IMPORT APReleaseSystemInit
    IMPORT GSMExit
    IMPORT magicInitVar

 [ :DEF: RTML
    IMPORT  TCB_Dummy
    IMPORT  TCB_CurrentTask
    IMPORT  Application_Initialize
 |
    IMPORT  TCD_System_Stack
    IMPORT  TCT_System_Limit
    IMPORT  INC_Initialize
 ]

    IMPORT |Load$$RAM_DATA$$Base|            
    IMPORT |Image$$RAM_DATA$$Base|         
    IMPORT |Image$$RAM_DATA$$Length|       
    IMPORT |Image$$RAM_DATA$$ZI$$Base|   
    IMPORT |Image$$RAM_DATA$$ZI$$Length| 
    IMPORT |Image$$RAM_DATA$$ZI$$Length|
    IMPORT |Image$$RAM_DATA$$ZI$$Length|

    IMPORT |Load$$IRAM_RO$$Base|           
    IMPORT |Image$$IRAM_RO$$Base|          
    IMPORT |Image$$IRAM_RO$$Length|        
    IMPORT |Image$$IRAM_RO$$ZI$$Base|   
    IMPORT |Image$$IRAM_RO$$ZI$$Length| 

    IMPORT |Load$$IRAM_RW$$Base|           
    IMPORT |Image$$IRAM_RW$$Base|          
    IMPORT |Image$$IRAM_RW$$Length|        
    IMPORT |Image$$IRAM_RW$$ZI$$Base|   
    IMPORT |Image$$IRAM_RW$$ZI$$Length| 


    IMPORT |Load$$RAM_CODE$$Base|        
    IMPORT |Image$$RAM_CODE$$Base|       
    IMPORT |Image$$RAM_CODE$$Length|     

    IMPORT WDResetStacks
    IMPORT WDResetRegisters    

    EXPORT DoVectorReset
    EXPORT End_of_Stacks
    EXPORT Initialize_memory_system
    EXPORT USR_Stack, End_of_Stacks, ABORT_Stack, ABORT_Stack_End








































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































SVC_STACK_SIZE    	EQU		0x1000
IRQ_STACK_SIZE    	EQU		0x400
FIQ_STACK_SIZE    	EQU		0x80
USR_STACK_SIZE    	EQU		0x80
UNDEF_STACK_SIZE    	EQU		0x80
ABORT_STACK_SIZE    	EQU		0x800


   AREA ADataForIRAM, DATA, READWRITE, NOINIT
   ALIGN

End_of_Stacks  							
SVC_Stack_End    % SVC_STACK_SIZE       	
SVC_Stack          							
IRQ_Stack_End     % IRQ_STACK_SIZE          	
IRQ_Stack                  						
FIQ_Stack_End   	% FIQ_STACK_SIZE		
FIQ_Stack          							
USR_Stack_End     % USR_STACK_SIZE        	
USR_Stack          							
UNDEF_Stack_End	% UNDEF_STACK_SIZE   	
UNDEF_Stack     							
ABORT_Stack_End	% ABORT_STACK_SIZE    	
ABORT_Stack                          				

  AREA    ExternalFlashSection, CODE, READONLY
  ENTRY
_ENTRY

DoVectorReset 

    MRS     a1,CPSR
    BIC     a1,a1,#0x1F
    ORR     a1,a1,#0x13
    ORR     a1,a1,#(0x80 | 0x40)
    MSR     CPSR_cxsf,a1

    MOV    r0,#0
    LDR    r1,=(0xFC130000 + 0x084)
    STR    r0,[r1]

    LDR     r0,=(0xFC130000 + 0x080)
    LDR     r0,[r0]
    TST     r0,#0x02
    BEQ    normal_start1

    LDR     r1,=WDResetRegisters
    LDR     r1,[r1]

    LDR     r0,=0xfc100060
    LDMIA   r0!,{r2-r11}
    STMIA   r1!,{r2-r11}

    LDMIA   r0!,{r2-r7}
    STMIA   r1!,{r2-r7}
    MOV      r13,r6                          

    LDR     r0,=0xfc10003c
    LDMIA   r0!,{r2-r10}
    STMIA   r1!,{r2-r10}

    LDR     r0,=0xfc10002c
    LDMIA   r0!,{r2-r5}
    STMIA   r1!,{r2-r5}

    LDR     r0,=0xfc10001c
    LDMIA   r0!,{r2-r5}
    STMIA   r1!,{r2-r5}

    LDR     r0,=0xfc10000c
    LDMIA   r0!,{r2-r5}
    STMIA   r1!,{r2-r5}

    LDR     r0,=0xfc100000
    LDMIA   r0!,{r2-r4}
    STMIA   r1!,{r2-r4}

normal_start1
   LDR     sp,=0xFC100000            
   LDR     r1,=|Image$$IRAM_RO$$Length|   
   CMP    r1,#0                                       
   BNE    C_Stack_1
   LDR    r1,=0x0000A000                         
C_Stack_1
   ADD    sp,sp,r1                                   


    LDR    r0,=1005
    LDR    r1, =(0x700C6000 + 0x02C)
    LDR    r1, [r1]
    TST    r1, #1<<3
    BNE    GSMExit

    BL InitialHWConfig

    LDR     r0,=(0xFC130000 + 0x080)
    LDR     r0,[r0]
    TST     r0,#0x02
    BEQ    normal_start2    

    LDR     r1,=WDResetRegisters
    LDR     r1,[r1]                  
    LDR     r1,[r1,#56]             
    LDR     r2,=WDResetStacks
    LDR     r2,[r2] 
    LDMIA   r1!,{r3-r12}                                 
    STMIA   r2!,{r3-r12}                                 
    LDMIA   r1!,{r3-r12}                               
    STMIA   r2!,{r3-r12}                             
    LDMIA   r1!,{r3-r12}                           
    STMIA   r2!,{r3-r12}                             
    LDMIA   r1!,{r3-r12}                           
    STMIA   r2!,{r3-r12}
    LDMIA   r1!,{r3-r12}  
    STMIA   r2!,{r3-r12}    
    LDMIA   r1!,{r3-r12}  
    STMIA   r2!,{r3-r12}    
    LDMIA   r1!,{r3-r6}    
    STMIA   r2!,{r3-r6}      

normal_start2
    BL Initialize_memory_system


    MOV    r0,#0xffffffff
    LDR    r1,=(0x700C1000 + 0x00C)
    STR    r0,[r1]

   mov   r4,#0x1f
   b     %1
0  mov   r0,#0
   mov   r1,r4,lsl #0x2
   add   r1,r1,#0x70000000
   add   r1,r1,#0xc1000
   str   r0,[r1,#0x18]
   sub   r4,r4,#0x1
1  cmp   r4,#0x0
   bgt   %0

    BL Initialize_IRAM

    BL Initialize_RAM_CODE    

    BL Setup_System_Stacks 


   BL APReleaseSystemInit

 [ :DEF: RTML
   BL Application_Initialize 
 |
   BL INC_Initialize 
 ]

Initialize_memory_system
    LDR    r0, =|Load$$RAM_DATA$$Base|        
    LDR    r1, =|Image$$RAM_DATA$$Base|       
    LDR    r3, =|Image$$RAM_DATA$$ZI$$Base|   

    CMP    r1, r3
    BEQ    %1
0   CMP    r1, r3
    LDRCC  r2, [r0], #4
    STRCC  r2, [r1], #4
    BCC    %0

1   LDR    r1, =|Image$$RAM_DATA$$ZI$$Base|       
    LDR    r2, =|Image$$RAM_DATA$$ZI$$Length|     
    ADD    r1, r1, r2
    SUB    r1, r1, #64                            
    MOV    r2, #0                        
2   CMP    r3, r1
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    STRCC  r2, [r3], #4
    BCC    %2
    LDR    r1, =|Image$$RAM_DATA$$ZI$$Base|       
    LDR    r2, =|Image$$RAM_DATA$$ZI$$Length|     
    ADD    r1, r1, r2                             
    MOV    r2, #0
3   CMP    r3, r1
    STRCC  r2, [r3], #4
    BCC    %3
    BX      LR


Initialize_IRAM

    LDR    r0,=(0xFC130000 + 0x60)
    LDR    r1,[r0]
    LDR    r3, =|pcu00bmcr0|
    STR    r1,[r3]
    ORR    r1,r1,#3
    STR    r1,[r0]

    LDR    r0, =|Load$$IRAM_RO$$Base|        
    LDR    r1, =|Image$$IRAM_RO$$Base|       
    LDR    r3, =|Image$$IRAM_RO$$ZI$$Base|   

    LDR    r2, =|IRAM_RO_StartPtr|
    STR    r1,[r2]

    CMP    r1, r3
    BEQ    %6
5   CMP    r1, r3
    LDRCC  r2, [r0], #4
    STRCC  r2, [r1], #4
    BCC    %5

6   LDR    r0,=|Image$$IRAM_RO$$ZI$$Base|
     LDR    r1,=|Image$$IRAM_RO$$ZI$$Length|

    LDR    r2, =|IRAM_RO_EndPtr|
    STR    r0,[r2]

     MOV    r2,#0
7   CMP    r1,r2 
     BEQ    %8
     STRB   r2,[r0],#1
     SUB    r1,r1,#1
     B      %7
8

    LDR    r0, =|Load$$IRAM_RW$$Base|        
    LDR    r1, =|Image$$IRAM_RW$$Base|       
    LDR    r3, =|Image$$IRAM_RW$$ZI$$Base|   

    CMP    r1, r3
    BEQ    %10
9   CMP    r1, r3
    LDRCC  r2, [r0], #4
    STRCC  r2, [r1], #4
    BCC    %9

10   LDR    r0,=|Image$$IRAM_RW$$ZI$$Base|
     LDR    r1,=|Image$$IRAM_RW$$ZI$$Length|
     MOV    r2,#0
11   CMP    r1,r2 
     BEQ    %12
     STRB   r2,[r0],#1
     SUB    r1,r1,#1
     B      %11
12
    BX      LR

Initialize_RAM_CODE
    LDR    r0,=|Load$$RAM_CODE$$Base|        
    LDR    r1,=|Image$$RAM_CODE$$Base|       
    LDR    r3,=|Image$$RAM_CODE$$Length|     

    ADD    r3,r1,r3                      
    CMP    r1,r3
    BEQ    %50
40   CMP    r1,r3
    LDRCC  r2,[r0],#4
    STRCC  r2,[r1],#4
    BCC    %40
50
    BX      LR

Setup_System_Stacks

    MOV    r1,lr

    MOV     r0, #0x17:OR:0x80:OR:0x40 
    MSR     cpsr_cxsf, r0
    LDR     sp, =ABORT_Stack
    LDR     sl, =ABORT_Stack_End

   MOV     r0, #0x1B:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =UNDEF_Stack
   LDR     sl, =UNDEF_Stack_End

   MOV     r0, #0x11:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =FIQ_Stack
   LDR     sl, =FIQ_Stack_End

   MOV     r0, #0x12:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =IRQ_Stack
   LDR     sl, =IRQ_Stack_End

   MOV     r0, #0x13:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0

 [ :DEF: RTML
   ldr     r13,=TCB_Dummy
   ldr     r0,=TCB_CurrentTask
   str     r13,[r0]

   LDR     sp, =SVC_Stack
   LDR     sl, =SVC_Stack_End   

 | 

   LDR     sp, =SVC_Stack
   LDR     r0, =TCD_System_Stack 
   STR     sp, [r0, #0] 
   LDR     sl, =SVC_Stack_End 
   LDR     r0, =TCT_System_Limit 
   STR     sl, [r0, #0]
 ]

   MOV     r0, #0x1F:OR:0x80:OR:0x40 
   MSR     cpsr_cxsf, r0
   LDR     sp, =USR_Stack
   LDR     sl, =USR_Stack_End

   MOV     r0, #0x13:OR:0x80:OR:0x40
   MSR     cpsr_cxsf, r0

   BX      r1


    END

